FPGA development for signal processing
Northwest DSP turns signal-processing algorithms into synthesizable designs that meet timing, fit the part and match the reference model bit for bit. The work covers architecture through hardware validation.
Common problems
Representative situations this work addresses. They describe the kind of work, not completed client projects.
The design does not fit the part
Architecture and fixed-point changes that recover DSP slices and block RAM.
Timing will not close at the target clock
Pipelining, retiming and clock-domain cleanup aimed at the failing paths.
Hardware output does not match the model
Bit-true test vectors that isolate the first point where the two diverge.
Builds are hard to reproduce
Scripted builds with version-controlled constraints and IP configuration.
Capabilities
Architecture and RTL
Designs built for streaming throughput and clean integration.
- SystemVerilog and VHDL
- Architecture and microarchitecture
- Streaming DSP pipelines
- AXI interfaces
Resource and timing
Making demanding algorithms fit the device and close timing.
- DSP-slice and block-RAM optimization
- Fixed-point arithmetic
- Timing closure
- Clock-domain crossing
Verification
Evidence that the hardware does what the model says.
- Bit-true comparison against the fixed-point model
- Simulation testbenches and stimulus
- Hardware-in-the-loop testing
- FPGA build automation
Typical deliverables
Scoped in each statement of work. You keep everything listed for your project.
- RTL source and constraints
- Vendor IP configuration
- Testbenches and stimulus files
- Synthesis and timing reports
- FPGA image
- Reproducible build instructions
Ways to start
FPGA optimization assessment
A review of an existing design's resources, timing and fixed-point choices, with ranked changes to recover margin.
Technical architecture review
An independent review of a proposed or existing signal chain, with findings and recommendations in a written report.
Prototype development
A working prototype of a waveform, modem or SDR function, carried from model to hardware within an agreed scope.
Each engagement is scoped and quoted in writing. See all ways to start.
Have a project in mind?
Describe what you are building and where you are stuck. You will hear back from Mike directly.
